Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr Analog/Mixed-Signal Design Engineer to join our Bufferchip Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.    As a Sr Analog/Mixed-Signal Design Engineer, the candidate will be reporting to the Sr. Director, Engineering and is a Full-Time position.Successful applicant will have highly visiblerole in product definition/design across Rambus sites.     Location: Agoura Hills, CA  

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior MTS Emulation Engineer to join our SOC team within the Memory Interface group in San Jose, CA. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   As a Senior MTS Emulation Engineering, the candidate will be reporting to Manager Emulation Engineering and is a Full-Time position. We are looking for an experienced “hands on” engineer in the areas of either emulation, validation or verification to join our dynamic and multi-disciplinary team focused on the emulation of our CXL memory products. In this role you will help to contribute to develop the emulation infrastructure, architecture, and methodologies as well as executing emulation build plans, compiling and making emulation builds, bring-up the SoC on the emulator, and execute the emulation testing. As an Emulation Engineer you will gain experience with processor-memory interfaces, including CXL and DDR topologies and protocols, as well as system level end to end testing of complex SoCs. The candidate will need to have strong organization, communication, teamwork, and debugging skills.

Rambus, a premier chip and silicon IP provider, is seekingto hire an exceptional Director of Validationto join our CXL SoCteam. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.    As a Director of Validation, the candidate will be reporting to the VP of Engineering and is a Full-Time position. We are looking for a highly technical director to join a dynamic and multi-disciplinary team focused on the validation of our CXL memory products. We are looking for an experienced “hands on” engineer who can improve our processes, methodologies, infrastructure, and help to grow the team to a best-in-class position.The ideal candidate will possess a wide range of technical skills involved in validating an SoC product starting from initial product concept through to the product release to production. The candidate should have comprehensive silicon and embedded firmware validation experience with a track record of successful tape-outs and first-pass success.  The candidate will need to have outstanding organization, communication, teamwork, debugging, and mentoring skills. 

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principle Field Applications Engineer to join our Security Sales team in Shangai, China. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   As a Sr. Principal Field Applications Engineer, the candidate will be reporting to Sr. Director of Field Applications Engineering in a Full-Time position.   Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.     The SPE Validation Engineer is a Full-Time position and the candidate will work in the lab to automate data collection and provide framework to develop validation environment to check system performance and specification compliance. The candidate will gain experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts.     Location(s): Atlanta, GA; San Jose, CA; Agoura Hills, CA; Chapel Hills, NC 

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Verification Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Layout Designto join our MIC Layout team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   As PE Layout Design, the candidate will be reporting to Layout Manager and is a Full-Time position. The MIC BU Layout team is a high-performance team gets involved in the complete development cycle starting with requirements, die area estimate, chip level floorplan, power, package discussions, execution of block level layouts, integration, physical verification, Database Transfer, e-Job review, and post-silicon support to multiple mixed signal designs which cater to market and revenue driven memory interface chips at Rambus Technologies.   Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.     The SPE Validation Engineer is a Full-Time position and the candidate will work in the lab to automate data collection and provide framework to develop validation environment to check system performance and specification compliance. The candidate will gain experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts.     Location(s): Atlanta, GA; San Jose, CA; Agoura Hills, CA; Chapel Hills, NC 

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interconnect Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   As a Principal Verification Engineer, the candidate will be reporting to the Director of Design Engineering and is a Full-Time position. Successful applicant will have highly visible role in product design across Rambus sites and take ownership of defining and executing verification plan for products.     Location: San Jose, CA or Remote (CA, NC, GA) 

Rambus, a premier chip and silicon IP provider, is seeking highly skilled Design Verification Engineer to lead our PCIe/ CXL (Compute Express Link) IP verification efforts. As the CXL IP Lead, you will be responsible for leading a team of verification engineers to ensure that our CXL IP meets the highest standards of quality and performance.  Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.   Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Analog/Mixed-Signal Design Engineer to join our Bufferchip Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.    As a Principal Analog/Mixed-Signal Design Engineer, the candidate will be reporting to the Director of Analog Design Engineering and is a Full-Time position.Successful applicant will have highly visiblerole in product definition/design across Rambus sites.     Location: San Jose, CA (Headquarters)