Rambus

Principal Engineer Logic Design - 6994

Job Locations US-OR-Hillsboro
Job ID
2020-6994
Category
Engineering

Responsibilities

  • Design architecting and trade-off analysis
  • RTL coding and verification
  • Controller + PHY integration and verification
  • FPGA targeting
  • Customer delivery and support

Qualifications

  • Strong Verilog RTL design and verification expertise
  • Questa/Incisive/VCS simulator experience
  • Python/Perl/Tcl scripting experience
  • Significant ASIC and/or FPGA design experience
  • Ability to learn quickly and work independently
  • Solid communication and project management skills
  • 5+ years of logic design experience

Definite Plus:

  • ASIC synthesis, timing constraint, CDC/RDC experience
  • Memory (HBM/DDR/LPDDR), PCI Express, or MIPI expertise
  • Located in the Portland, Oregon area

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