At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors and lighting. Our products are integrated into billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, and consumer platforms.
And our history runs deep – we have been a staple in Silicon Valley since 1990 and are continually anticipating key technology trends to develop innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker and developer of innovative software solutions, Rambus is evolving to address critical challenges throughout the industry.
As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real-life impact. As well, Rambus benefits are among the most comprehensive and competitive in the market today.
You will assume both “hands-on” and leadership roles in the design of DDR5 memory buffer chips. You will be responsible for the successful execution of critical chip sub-systems and work in a team through all phases of development including specification, design, verification, and silicon evaluation. The primary focus of the position is transistor-level design of high performance and low power mixed-signal circuits in CMOS, which may include chip IO (Tx/Rx), clock synthesis and distribution (PLL/DLL), adjustable timing circuits (DCDL), voltage regulators, ESD, equalizers, crosstalk cancellation, etc. In addition to analog circuit expertise, job responsibilities include custom logic design, familiarity with static timing analysis, and proficiency in the construction of behavioral models using Verilog and Verilog-A. Furthermore, you will be called upon to both utilize and contribute to the development of tools, scripts, and design flows for robust validation of analog/digital interfaces. Other responsibilities include layout supervision, technical documentation, customer interaction and data preparation, presentation of results and evaluation of peer results in design reviews.