Rambus is looking for a highly motivated Signal Integrity Engineer working on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) of high-speed memory interfaces.

In this highly visible role, the candidate will create SI/PI methodologies and run simulations for the latest memory interfaces for our IP portfolio.  These interfaces include the latest GDDR6 16Gig, DDR5 6.4Gig and HBM3.0 (and much more).  You will work with our design team to define specifications and system design requirements such are packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis.  You will help Rambus’ customers through the implementation of the IP and help application engineers during debug and bring up in lab if needed.  You will have the opportunity to work on new memory initiatives, use your creativity to enable the industry for the next generation of IOs and SerDes which will enable the servers, autonomous cars, AI and networking.

Requirements:

• Electrical Engineering degree with emphasis on electromagnetics (EM), SI, PI, Analog, RF or advanced packaging
• Prior experience simulating at least two types of memory interfaces is required (i.e. DDR4, DDR5, GDDR5/6, HBM2/3, LPDDR4/5)
• Solid theoretical background and understanding in EM and transmission line theory is a must
• Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system.
• Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
• The candidate should be proficient with simulations using Spice and ADS
• Understanding of equalization techniques such as FIR/DFE/CTLE is needed
• Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
• Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
• Lab characterization experience of passive components, link margin, or noise using realtime and sampling scopes and using VNA/TDR is a big plus
• Basic knowledge of circuits used in high-speed link design is preferred.
• Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functionally

10yrs, Masters