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- Perform RTL-level design, including micro-architectural definition, of digital logic used in secure ASIC cores.
- Assist with EDA tool-related tasks, such as synthesis, static-timing analysis, logical equivalency checking, and help improve flows and scripts for such tasks.
- Assist with integration of CRD technology into customer and partner ASIC design projects, in such areas as clocking and reset logic, memory interfaces, test interfaces, and system buses.
- BE/Btech/ME/Mtech degree in electronics engineering
- Experience: Minimum 10 years of experience
- Understanding of front-end ASIC design flows, including design, simulation, synthesis, and timing analysis. Experience with back-end flows, especially place-and-route, is beneficial.
- Very high technical competence that includes a track record of on-time delivery of silicon-proven designs.
- Very high degree of skill with Verilog and digital design.
- Expertise in some or all of the following areas is beneficial:
- IP core delivery and handoff issues
- Modern SoC design methodologies and architectures.
- DFT, especially memory testing and characterization and/or Logic BIST methodologies.
- Manufacturing test, device characterization and qualification, reliability testing.
- Hardware development experience in UNIX/Linux environments, including supporting tasks such as shell scripting and basic Perl scripts.
- Ability to work with technical writers in the production of technical documentation.
- Personal Attributes
- Excellent written, verbal, and interpersonal communication skills.
- Able to communicate ideas in both technical and user-friendly language.
- Able and willing to work in a team-oriented, collaborative environment, cross functional and across sites.
- Highly self-motivated and directed, with keen attention to detail.
- A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment
- Proven analytical and creative problem-solving abilities.
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