Take complete ownership for Timing Analysis & Signoff of Test-chip Top level and Block level designs
Responsible for independent planning and execution of all aspects of Timing Signoff including Timing Constraints development, Static Timing Analysis, IP timing, Chip level Timing closure, Signal Integrity Analysis, Tape Out Timing Signoff on 28nm nodes or below.
Must coordinate with design team counterparts in System/RTL design, IP design and Physical design
Hands-on experience in chip level timing analysis (STA), timing closure methodologies, timing corners, modes and process variations
Should be able to provide clear directions to the team with regards to Timing issues
Role involves tasks in time-budgeting using industry standard tool
Knowledge of low power techniques including clock-gating, power-gating and multi-voltage designs
Must be experienced with timing closure methodologies such as OCV/AOCV/Statistical Timing and Signal Integrity issues
Must be a good team player with good oral, written and verbal communication skill. Must be able to negotiate with cross-functional teams for convergence.
Work closely with Principal Engineer / Project leader for creating schedule, tracking and raising issues / risks to project management.
Participate in Mentoring new hires in the group on technical skills.
Provide inputs for CAD/DA team from Design Implementation perspective.
Skills & Qualification:
Must have minimum Bachelor’s degree in EE from a reputed institute.
Must have at least 5 – 8 years of experience, out of which at least 4 years should be related to timing signoff at chip level / block level
Must have implemented and completed a minimum of 4 to 6 design tapeouts. Understanding of multi-mode multi-corner timing in FINFET nodes (14/10/7nm) using Multi-Vt libraries
Must have detailed knowledge of EDA tools and flows. Synopsys Primetime-SI, Synopsys Design Compiler, Cadence RC/Genus. Desirable Synopsys ICC, Cadence Encounter/Innovus
Proficient in Tcl/Tk, Perl scripting
Synthesis /STA experience in peripherals such as I2C, SPI, UART, Asynchronous interface designs, interconnect protocols such as AHB, AXI, PCIE, etc., is an added advantage.
Desirable experience in formal / logic equivalence checking techniques