SMTS,Logic Verification Engineering

Job Locations IN-KA-Bangalore
Job ID


Roles & Responsibilities :

  • Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers and post-silicon teams



  • Bachelor's/Master's degree in Electronics/Electrical Engineering
  • 5+ years of verification experience
  • Significant experience in HVL based verification with 2+ years expertise in SV & OVM
  • Experience in DDR3/4/5 memory protocol knowledge
  • Good understanding of memory technology and memory sub-system
  • Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex designs
  • Should have knowledge on all aspects of verification components & verification closure
  • Should have flair for documentation, defining/improving methodology and achieving productivity improvement
  • Ability to provide technical guidance & resolving technical conflicts desired
  • Ability to communicate technical and project issues to business and technical senior management
  • MUST have very good verbal and written communication skills


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