Lead complete ownership of IP physical implementation, integration and TC implementation till TO.
Take complete ownership for implementation of Testchip Top level and Block level designs
Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below.
Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
Well versed with the level timing closure (STA), timing closure methodologies.
Should be able to provide clear directions to the team on PnR flows.
Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification
Working on very leading technology nodes: 14nm, 10nm, 7nm.
Responsible for integrating the top level IP, and collateral deliverables to the customer.
Well aware of place and route methodologies and hands on experience with timing convergence
Good communication skill to negotiate with top level for convergence.
Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management.
Participate in Mentoring new joinees in the group on technical skills.
Provide inputs for CAD/DA team from Design Implementation perspective.
Work closely with DFT team on scan aspects and provide inputs from physical design.
Continuously work on methodology and productivity improvements.
Skills & Qualification:
Must have minimum Bachelors degree in EE from a reputed institute.
Must have atleast 10 – 12 years of experience, out of which atleast 8 years should be related to physical design at chip level / block level.
Must have implemented and completed a minimum of 8 design tapeouts.
Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
Experience in Tcl/Tk, PERL is a Plus
Synthesis experience and exposure besides chip implementation flows is an added advantage