Knowledge of packet based protocol
Expertise/ understanding in digital designs
Hands on experience with complete ASIC flow is required
Good knowledge of Synthesis, DFT and Timing closure requirements.
Should have good exposure to the FPGA flow.
Should have exposure to verification flow and concepts
Masters degree in Electronics (Microelectronics specialization preferred)
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.