In this position the person will be responsible to develop and design the high speed circuit blocks used in Rambus proprietary advanced development projects and JEDEC standard based physical (PHY) layers. These physical layers are the high speed mixed signal blocks, designed in advanced technology node such as 65nm, 40nm and 28nm. The knowledge and experience in high speed receivers, equalization techniques, samplers, transmitters, multi clock domain custom digital data-path circuits and clocking circuits are necessary. The designer will be responsible for all aspects of designs such as schematic capture, layout review, simulation & analysis of critical electrical and timing parameters, documentation and silicon bring-up.
MS/M-Tech degree in electronics/VLSI with some relevant experience needed.
The candidate should have prior experience of high speed custom circuit design. The senior position requires demonstrated ability to have worked in these domains and a sound understanding of the standards, protocols, practical aspects of circuit design in DSM process nodes ( 28nm, 16nm,14nm) are very desirable.
Strong fundamental knowledge is essential. Sound knowledge of basic building blocks (Ex: bias generation, on-chip regulation, on-chip impedance circuits and PLL) is highly desirable.
Experience in designing memory interfaces such as DDR/3/4 and LP3/4 or serial links such as USB/XAUI/, CEI6/ LVDS /PCIE//SATA and Display Port etc.)
Experience working in leading R&D and future technology development projects is desirable.
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams