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At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors and lighting. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

And our history runs deep – we have been a staple in the Silicon Valley, California for the past 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact.

Memory and interfaces are in our DNA. Leveraging over two decades of high-speed circuit design leadership, we make high-performance, low-power memory and serial link interface chips and IP cores to meet the needs of increasingly diverse enterprise and mobile applications. Featuring proven IP and advanced technology, our product families include server DIMM chipsets, R+ DDRn PHYs and R+ Serial Link PHYs.



The Physical Design Engineer (all levels) will assume an implementation & design role at Rambus. The primary activity will be Schematic to GDSII implementation driving the design from Floor planning through Post-Layout. The successful candidate will also support developing, deploying, and supporting analog and physical design methodologies and flows associated with the design of high speed mixed-signal ICs.

  • Responsible for physical implementation of analog and digital blocks for mixed signal designs
  • Ownership of floor planning, abstract creation, new layout, porting and other modifications to existing layout, routing, and place & route merges, signal integrity analysis, extraction, EM/IR fixes & physical verification,
  • Mentor junior engineers by providing technical direction in physical design

Methods Support: 

  • Develop and support nanometric CMOS physical design flow
  • Develop and maintain Mixed Signal physical design methodology
  • Evolve and Support the Schematic/RTL 2 GDSII flow
  • Maintain Technology environment, std cell and custom IP libraries
  • Support physical verification environment





  • Familiar with Layout Editors, Schematic and CAD Tools for nanometric Technologies
  • Preferred candidate has experience on FinFET Technologies
  • Knowledge of high speed analog design fundamentals
  • Excellent verbal and written communication skills
  • Self-motivated, excellent attention to detail, strong problem solving and presentation skills.
  • Highly motivated and committed to success of design teams and projects
  • Preferred candidate has MASc or BASc in Electrical Engineering or equivalent degree
  • Preferred candidate has experience on Cadece, SKILL programming, Mentor Calibre DRC/LVS




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