SMTS II,Circuit Design Engineering - Digital

Job ID


We are searching for Digital Designer for design and development of ASIC’s/SOCs in CMOS on leading edge silicon technologies. Job activities include Architecture, Design, Simulation, Documentation, Verification, Validation, FPGA porting.  Candidates should have experience working with state-of-the-art industry tools and ASIC methodologies



  • Will be doing RTL (Verilog) coding and verification of the design using Verilog
  • Working with SOC/ASIC team defining, architecting and development of RTL blocks
  • Working with IP teams and integration of IP.
  • Working on FPGA emulations, and design validation using FPGAs & Emulators
  • Will be doing design synthesis, STA DFT




  • BS or MS in Electrical Engineering with a minimum 7 years of experience
  • Hands on experience with Cadence, Synopsys & Mentor EDA tools
  • Proficient with RTL Logic Design, Verification, Synthesis, DFT & STA
  • Experience with at least one of Serial protocols (PCIe, USB or SATA)
  • Should be familiar with I2C ( SMbus) and/or SPI interfaces
  • Working knowledge with PCIe protocol is plus
  • Working with 8/16/32-bit CPU subsystem is plus
  • Experience working in technologies on 90nm or smaller CMOS process node is plus
  • Must have good communication skills



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