This is a highly visible and impactful position inside the Solutions Architecture team, Memory and Interfaces Division. The key role is develop advanced DSP for 112G/56G SerDes PHY with an emphasis on very low-power and low-latency design. The individual will design DSP/digital-based FFE, DFE, and MLSE components, and will work together with design teams to ensure that the component designs conform to the micro-architecture intent, both in performance and implementation approach. Will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. Must be a team player with excellent written and verbal communication skills; must be self-motivated and detail-oriented and have the ability to work with peers across groups and projects.