SPE,Circuit Design Engineering

US-CA-Sunnyvale
Job ID
2017-5993
Category
Engineering

Overview

This is a highly impactful position inside the Solutions Architecture team, Memory and Interfaces Division. The key role is to design advanced global and local clocking schemes for 112G/56G SerDes PHY with an emphasis on low-power and low-jitter design. The individual will design clock synthesizers (PLL/DLL) utilizing LC resonant structures, global and local clock distributions, and phase interpolator for clock data recovery (CDR). Will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. Must be a team player with excellent written and verbal communication skills; must be self-motivated and detail-oriented and have the ability to work with peers across groups and projects.

Responsibilities

 

  • Develop micro-architecture for components in advanced 112G/56G serial links. Signaling scheme includes NRZ and PAM4.
  • Design clock synthesizers (PLL/DLL), clock distributions, phase interpolator, clock data recovery (CDR)
  • Other design responsibilities may include ADC, receiver AFE (ESD, T-coils & termination, CTLE, VGA, FFE), current/voltage-mode drivers, bias circuits, regulators, and serializers/deserializers
  • Layout guidance and supervision
  • Generate innovative solutions that can be brought to market and protected by patents
  • Demonstrate proof-of-concepts through prototyping in advanced 7/10-nm FinFET processes. Silicon debug and evaluation.
  • Participation in technology evangelization through customer presentation, conference and journal publications

Qualifications

 

  • MS or Ph.D. degree in Electrical Engineering
  • 5 to 10+ years of industry experience
  • Architecture and design experience in high-performance and low-power serial links
  • Design experience in PLL, DLL, Phase Interpolator, and CDR is a must. Design experience with ADC, receiver AFE, driver, custom digital circuits, and general mixed-signal components is highly desirable.
  • Must be familiar with layout extraction, EMIR, matching techniques
  • Working knowledge of communication theory, signal integrity, noise analysis, BER link analysis, and equalization techniques is necessary
  • Requires experience with the following tools: Matlab & Simulink modeling tool, Cadence Virtuoso, Hspice/Spectre, Nanosim/XA, Verilog-A, and DRC & LVS verification. Shell scripting and programming experience are highly desirable.
  • Must be able to work with a diverse team of specialists and understand overall tradeoffs in creating complex, high performance systems
  • Excellent written and oral communication skills

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