This is a highly impactful position inside the Solutions Architecture team, Memory and Interfaces Division. The key role is to design advanced global and local clocking schemes for 112G/56G SerDes PHY with an emphasis on low-power and low-jitter design. The individual will design clock synthesizers (PLL/DLL) utilizing LC resonant structures, global and local clock distributions, and phase interpolator for clock data recovery (CDR). Will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. Must be a team player with excellent written and verbal communication skills; must be self-motivated and detail-oriented and have the ability to work with peers across groups and projects.