This is a highly impactful position inside the Solutions Architecture team, Memory and Interfaces Division. The key role is to design receiver analog front-end (AFE) components for 112G/56G SerDes PHY with an emphasis on high gain and bandwidth, high linearity, low jitter, and low power. The individual will design ESD and T-coil based termination, analog-based CTLE, VGA, and FFE equalizers. Will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. Must be a team player with excellent written and verbal communication skills; must be self-motivated and detail-oriented and have the ability to work with peers across groups and projects.