This is a highly impactful position inside the Solutions Architecture team, Memory and Interfaces Division. The key role is to design analog-to-digital converters (ADC) for 112G/56G SerDes PHY with an emphasis on high sampling rate and low power. The individual will perform feasibility on ADC architectures (e.g. flash, SAR, pipeline) to determine most optimal architecture, and design for ADC components such as interleavers, reference circuit, samplers, decimators, re-timers, and internal ADC clocking. Will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. Must be a team player with excellent written and verbal communication skills; must be self-motivated and detail-oriented and have the ability to work with peers across groups and projects.