• MTS ,Systems Design Engineering

    Job Locations IN-KA-Bangalore
    Job ID
  • Responsibilities


    • Will be responsible for Validating  and System bring-up of SOC chips with high Speed SERDES.

    This includes

    • Developing Test plan & Test methods to validate Digital SOC’s Products (which include high speed SERDES and micro controllers)
    • Bring-up & Debug of SOC chips.
    • Debugging SOC designs in FPGA’s.
    • Create test scripts & automation
    • Debug failures, work with cross functional teams (Design, Verification, Sofware, Application) to root cause issues and find solutions or workarounds.
    • Test Report Generation & Technical support for Internal & External Customers
    • Provide technical assistance to Application team on any customer/Field issues



    • Must have minimum Bachelor’s degree in EEE/ECE or Master Degree from a reputed institute.
    • Must have 7+ years of work experience with SOC’s validation which includes high speed SERDES
    • Experience & strong knowledge in PCIe experience is required. USB and SATA Protocol is plus.
    • Must have Expertise in SERDES protocol for PCIe Gen1,2,3  PMA, PCS and MAC layer and associated debug.
    • Knowledge of PCIe root complex design.
    • Experience in using Automation Tools & Lab equipment’s like PCIe Protocol Analyzers/exercisers, BERTs, Multimeter, Pattern generators, DSO oscilloscopes.
    • Exposure to PCB design & cadence PCB development tools.
    • He should have working experience with Verilog and C.
    • Very strong programming and scripting skills.
    • Good communications and interpersonal skills.


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