PE - Technical Lead of ASIC Engineering

Job ID



At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors and lighting. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

And our history runs deep – we have been a staple in Silicon Valley for the past 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

The Rambus Security Division (RSD) is dedicated to providing a secure foundation for a connected world. Integrating technologies from Cryptography Research, Bell ID and Ecebs, our innovative solutions span areas including tamper resistance, content and media protection, network security, mobile payment, smart ticketing, and trusted transaction services. Our technologies protect nearly nine billion licensed products annually, providing secure access to data and creating an economy of digital trust between our customers and their customer base. As a premier provider of security solutions, the Rambus Security Division focuses on market sectors that present opportunities for rapid deployment of innovative technologies to meet consumer needs.


Rambus is seeking a dynamic, highly motivated, experienced Senior Digital Design Engineer. The ideal candidate will be team oriented, highly skilled on digital design in deep nanometer technology nodes ICs and FPGA environment, and very proficient with all most advanced EDA tools.


She/he will have a strong knowledge of the complete vertical digital design process and related design flows, from Front-End to Back-End, and a well-proven industrial experience designing digital security IPs and IC products.

She/he will also provide hands-on support on design tools and technical tasks to the other members of the team.




  • Takes ownership and leadership in designing, verifying and validating complex secure digital IPs in deep nanometer technology nodes
  • Supervise and technical lead of digital developments (technical management, planning follow-up, hands-on support to other Designers) while being directly involved in design tasks
  • Promotes and implements best practices in digital design: component, IP, platform-based structured design, design re-use, Design-For-Testability (DFT), Universal Verification Methodology (UVM), verification and validation plans with their synergies (V&V), non-regression testing, revision control and bug tracking
  • Help define and drive tool flows and CAD methodology
  • Documentation: Technical Specifications, IP Datasheets, Verification and Validation Plans, Test Reports, Patents, Scientific Publications



Required Skills

  • 8+ years of hands-on ASIC development
  • RTL, HDL Coding (Verilog, System Verilog)
  • Strong skills in at least one scripting language (Perl, Python)
  • Simulation and Debug Tools
  • Synthesis, lint and LEC tools
  • Static timing analysis and signal integrity
  • Floor planning and clock tree synthesis planning
  • FPGA Synthesis and Place & Route
  • Strong drive, dynamic, proactive, takes initiative to “raise the bar”
  • Excellent (English) verbal/oral communication and documentation skills
  • Proven track record of taking ownership and driving results
  • Demonstrated ability to conceptualize, lead/manage, and prioritize multiple projects

 Educational Requirements 

  • Bachelor (Master preferred) in Electrical Engineering or Computer Science

 Preferred Skills

  • Knowledge of HW security architectures and IPs (secure MCU cores, cryptographic co-processors, secure memories, sensors, detectors, secure elements, smart cards)
  • Architecture definition, sizing and behavioral modeling (C, C++, Matlab)
  • DFT, scan insertion, ATPG tools (DFTMAX, Tetramax)
  • UVM Verification methodology, debug tools (Verdi)



Rambus offers an extremely competitive compensation package, which includes a strong base salary, bonus, equity, and employee stock purchase plan.

Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit For additional information on life at Rambus and our current openings, check out



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