PE ,ASIC Verification Engineering

IN-KA-Bangalore
Job ID
2016-5468
Category
Engineering

Responsibilities

Roles & Responsibilities

  • Co-ownership of Verification Testbench written in SystemVerilog and/or  C/C++
  • Architect verification Testbench for new IP/Products by leveraging existing test benches, methodologies and industry best known practices
  • Handle block/Module/IP level verification independently.
  • Create various verification components in C/C++, SystemVerilog and using related methodology guidelines
  • Debug issues and present / discuss problems with designers independently
  • Run regression, analysis reports, achieve code coverage and functional coverage goals
  • Run netlist verification without and with SDF
  • Create Verification plans and other documents required for the project.
  • Provide technical guidance to team and also provide mentorship
  • Develop tools/Automation to improve the efficiency of verification and closure
  • Stay current with latest tools, technology ideas and methodologies; share knowledge by clearly articulating results and ideas to key decision makers.

Qualifications

Skills, Qualification and Experience :

·         Possess MS/MTech in Electronics/VLSI Engineering with Minimum 7+ years’ experience in ASIC Design Verification

·         Good understanding of computer architecture and ability to understand complex micro-architectures

·         Strong programming skills and understanding of one or more Processor of, SPARC, MIPS, ARM, X86 and PowerPC

·         At least 3+ years of Core processor verification/ISA verification

·         Experience in IP, Chip and/or SoC level verification

·         Knowledge and Verification of hardware Cryptography IP is a plus

·         Knowledge of standard interfaces viz., AXI, AHB, is a plus

·         Strong Verilog, System Verilog, PLI/DPI interface, C/C++ hands on experience

·         Proficiency in one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc. is a great plus

·         Experience in advanced verification methodologies such as coverage driven, assertion and formal verification

·         Experience with verification reuse methodologies such as UVM/OVM,VMM and eRM

·         Experience in developing complex test bench/model in Verilog, System Verilog & C/C++

·         Experience in writing test plans and test cases

·         Experience with C/ASM based tests

·         Excellent hands-on debug skills

·         Must have good communication & interpersonal skills.

·         Independent, self-motivated, professional attitude and strong desire to succeed

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