Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interface chips team in Bangalore . In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

As a Principal Verification Engineer, you’ll play a pivotal role in (DDR Verification, starting from understanding the design till Verification sign-off, and also to support the Validation team post-tapeouts ). In this full time role, you’ll report directly to our Senior Director. Our MIC team is dedicated to produce high speed DDR products at a high quality to meet the industry requirements, and your contributions will be instrumental in closing the Verification requirements of these products.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work

• Understand the product requirements from the specifications and beyond
• Planning and execution to meet the verification sign-off criteria
• Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system using UVM methodology
• Guide and mentor the team to meet the sign-off requirements Work with architects, designers and post-silicon teams

• Bachelor's or Master's degree in Electronics with 10+ years of relevant experience
• Expertise in System verilog and UVM
• Strong debugging skills
• Experience in all verification aspects from understanding the design requirements till sign-off
• Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex designs
• Ability to communicate technical and project issues to business and technical senior management.
• Must have very good verbal and written communication skills
• Experience in I2C/I3C Protocol & DDR3/4/5 memory protocol knowledge (preferrable)