Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineer – Logic Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Principal Engineer – Logic Design, the candidate will be reporting to Director Engineering and is a Full-Time The candidate will be leading all the digital logic design activities for high-performance mixed signal chip products. Rambus memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production.

As a “Principal Engineer – Logic Design” in memory interface chip design team, you will

• Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products.
• Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain crossing etc.) and timing closure.
• Develop various analog behavioral models for analog custom blocks to enable high digital verification coverage.
• Collaborate with verification team to ensure implementation meets both architectural and micro-architectural intent.
• Interface with physical design, design for test, co-simulation & timing teams to optimize tradeoffs within the design.
• Drive for power, performance, and area (PPA) targets or enhancements.
• Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion.
• Participate and drive post silicon validation, debug, and customer collaboration.

• Master’s with 8+ years (or bachelor’s with 10+ years) of experience in micro-architecture, RTL design, Synthesis, and timing closure for designs using multiple clock domains.
• Experience coding within Verilog and/or System Verilog along with scripting languages such as Shell, Tcl, or Python.
• Experience with low power design techniques and methodologies
• Knowledge of high-speed chip to chip interfaces (memory PHY, SerDes) is a strong plus.
• Experience in mixed signal designs is preferred.

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

  
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.