Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead or Principal Physical Design Engineer to join our Memory Interface chip Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Lead or Principal Physical Design Engineer, the candidate will be reporting to the Sr. Director, Engineering and is a Full-Time position. Successful applicant will have highly visible role in product definition/design across Rambus sites.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

• Ownership of Analog/Mixed designs at chip and/or block level
• Define optimal architectures to achieve competitive product specifications.
• Perform partition synthesis and physical implementation steps (e.g. synthesis, floor-planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Characterize Analog IP with tools such as Nanotime/Silicon Smart etc.
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

PREFERRED SKILLS AND EXPERIENCE:

• Experience of ASIC/SOCs RTL2GDSII physical design and signoff flows
• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

Requirements/Qualifications:

• MS EE and 7+ years or PhD EE and 5+ years’ experience of CMOS analog/mixed-signal circuit design. Position may be tailored appropriately with different level of experience.
• Good knowledge of design principles for practical design tradeoffs
• Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is desirable
• Prior design experience in FinFET process and digitally assisted design is desirable
• Experience in modeling with matlab, Verilog-A, verilog is desirable
• Experience working in leading R&D and future technology development projects is desirable
• The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
   

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

The US salary range for this full-time position is $141,300.00 to $191,100.00.  Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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